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CA5160
NOT RECOMMENDED FOR NEW DESIGNS
September 1998
4MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output
Description
CA5160 is an integrated circuit operational amplifier that combines the advantage of both CMOS and bipolar transistors on a monolithic chip. The CA5160 is a frequency compensated version of the popular CA5130 series. It is designed and guaranteed to operate in microprocessor or logic systems that use +5V supplies. Gate-protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very high input impedance, very low input current, and exceptional speed performance. The use of PMOS field effect transistors in the input stage results in common-mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute in single supply applications. A complementary symmetry MOS (CMOS) transistor pair, capable of swinging the output voltage to within 10mV of either supply voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA5160 operates at supply voltages ranging from +5V to +16V, or 2.5V to 8V when using split supplies, and have terminals for adjustment of offset voltage for applications requiring offset-null capability. Terminal provisions are also made to permit strobing of the output stage. It has guaranteed specifications for 5V operation over the full military temperature range of -55oC to 125oC.
Features
* MOSFET Input Stage - Very High ZI; 1.5T (1.5 x 1012) (Typ) - Very Low II; 5pA (Typ) at 15V Operation 2pA (Typ) at 5V Operation * Common-Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail * CMOS Output Stage Permits Signal Swing to Either (or Both) Supply Rails * CA5160 Has Full Military Temperature Range Guaranteed Specifications for V+ = 5V * CA5160 is Guaranteed to Operate Down to 4.5V for AOL * CA5160 is Guaranteed Up to 7.5V
Applications
* Ground Referenced Single Supply Amplifiers * Fast Sample-Hold Amplifiers * Long Duration Timers/Monostables * Ideal Interface With Digital CMOS * High Input Impedance Wideband Amplifiers * Voltage Followers (e.g., Follower for Single Supply D/A Converter) * Wien-Bridge Oscillators * Voltage Controlled Oscillators * Photo Diode Sensor Amplifiers * 5V Logic Systems * Microprocessor Interface
Ordering Information
PART NUMBER (BRAND) CA5160E CA5160M96 (5160) TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 8 Ld PDIP 8 Ld SOIC Tape and Reel PKG. NO. E8.3 M8.15
Pinout
CA5160 (PDIP, SOIC) TOP VIEW
OFFSET NULL INV. INPUT NON INV. INPUT V-
1 2 3 4
8 7 6 5
STROBE V+ OUTPUT OFFSET NULL
+
NOTE: CA5160 devices have an on-chip frequency compensation network. Supplementary phase-compensation or frequency roll-off (if desired) can be connected externally between terminals 1 and 8.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
1924.4
3-1
CA5160
Absolute Maximum Ratings
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 165 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. Short circuit may be applied to ground or to either supply.
Electrical Specifications
TA = 25oC, V+ = 5V, V- = 0V, Unless Otherwise Specified TEST CONDITIONS VO = 2.5V VO = 2.5V VO = 2.5V VCM = 0 to 1V VCM = 0 to 2.5V CA5160 MIN 70 60 2.5 V+ = 1V; V- = 1V RL= RL=10k ISOURCE ISINK VOUT VO = 0V VO = 5V RL = 55 95 85 1.0 1.0 4.99 RL = 10k 4.4 RL = 2k 2.5 ISUPPLY ISUPPLY VO = 0V VO = 2.5V TYP 2 0.1 2 80 69 2.8 -0.5 67 117 102 3.4 2.2 5 0 4.7 0 3.3 0 50 320 MAX 10 10 15 0 4.0 4.0 0.01 0.01 0.01 100 400 UNITS mV pA pA dB dB V V dB dB dB mA mA V V V V V V A A
PARAMETER Input Offset Voltage Input Offset Current Input Current Common Mode Rejection Ratio
SYMBOL VIO IIO II CMRR
Common Mode Input Voltage Range
VlCR+ VlCR-
Power Supply Rejection Ratio Large Signal Voltage Gain (Note 3) Source Current Sink Current Maximum Output Voltage VOM+ VOMVOM+ VOMVOM+ VOMSupply Current VO = 0.1 to 4.1V VO = 0.1 to 3.6V
PSRR AOL
NOTE: 3. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10k.
Electrical Specifications
TA = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified TEST CONDITIONS VO = 2.5V VO = 2.5 V CA5160 MIN TYP 3 0.1 MAX 15 10 UNITS mV nA
PARAMETER Input Offset Voltage Input Offset Current
SYMBOL VIO IIO
3-2
CA5160
Electrical Specifications
TA = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified (Continued) TEST CONDITIONS VO = 2.5V VCM = 0 to 1V VCM = 0 to 2.5V Common Mode Input Voltage Range VlCR+ VlCRPower Supply Rejection Ratio Large Signal Voltage Gain (Note 4) Source Current Sink Current Maximum Output Voltage VOM+ VOMVOM+ VOMVOM+ VOMSupply Current VO = 0V VO = 2.5V NOTE: 4. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10k. ISUPPLY ISUPPLY RL = 2k RL = 10k VO = 0.1 to 4.1V VO = 0.1 to 3.6V ISOURCE ISINK VOUT PSRR AOL V+ = 2V RL= RL=10k VO = 0V VO = 5V RL= CA5160 MIN 60 50 2.5 40 90 75 0.6 0.6 4.99 4.0 2.0 TYP 2 80 75 2.8 -0.5 60 110 100 5 0 4.3 0 2.5 0 170 410 MAX 15 0 5.0 5.0 0.01 0.01 0.01 220 500 UNITS nA dB dB V V dB dB dB mA mA V V V V V V A A
PARAMETER Input Current Common Mode Rejection Ratio
SYMBOL II CMRR
Electrical Specifications
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified TEST CONDITIONS VS = 7.5V VS = 7.5V VS = 7.5V VO = 10VP-P RL = 2k CA5160 MIN 50 94 70 10 V+ = 1V; V- = 1V VS = 7.5V RL = 2k 12 RL = 14.99 TYP 6 0.5 5 320 110 90 -0.5 to 12 32 13.3 0.002 15 0 MAX 15 30 50 0 320 0.01 0.1 UNITS mV pA pA kV/V dB dB V V/V V V V V
PARAMETER Input Offset Voltage Input Offset Current Input Current Large Signal Voltage Gain
SYMBOL VIO IIO II AOL
Common Mode Rejection Ratio Common Mode Input Voltage Range Power Supply Rejection Ratio Maximum Output Voltage VOM+ VOMVOM+ VOM-
CMRR VlCR PSRR VOUT
3-3
CA5160
Electrical Specifications
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued) TEST CONDITIONS VO = 0V VO = 15V I+ RL = , VO = 7.5V RL = , VO = 0V Input Offset Voltage Temperature Drift VIO/T CA5160 MIN 12 12 TYP 22 20 10 2 8 MAX 45 45 15 3 UNITS mA mA mA mA V/oC
PARAMETER Maximum Output Current Supply Current IOM+ (Source) IOM- (Sink)
SYMBOL IO
Electrical Specifications
For Design Guidance, At TA = 25oC, VSUPPLY = 7.5V, Unless Otherwise Specified TYPICAL VALUES
PARAMETER Input Offset Voltage Adjustment Range Input Resistance Input Capacitance Equivalent Input Noise Voltage
SYMBOL
TEST CONDITIONS 10k Across Terminals 4 and 5 or 4 and 1
CA5160 22 1.5
UNITS mV T pF V V nV/Hz nV/Hz MHz V/s s % s
RI CI eN f = 1MHz BW = 0.2MHz, RS = 1M BW = 0.2MHz, RS = 10M
4.3 40 50 72 30 4 10
Equivalent Input Noise Voltage
eN
RS = 100, 1kHz RS = 100, 10kHz
Unity Gain Crossover Frequency Slew Rate Transient Response Rise Time Overshoot Settling Time (To <0.1%, VIN = 4VP-P)
fT SR tR OS tS CC = 25pF, RL = 2k, (Voltage Follower) CC = 25pF, RL = 2k (Voltage Follower)
0.09 10 1.8
Block Diagram
7 200A 1.35mA 200A 8mA (NOTE 5) 0mA (NOTE 6) V+
BIAS CKT.
NOTE: 5. Total supply voltage (for indicated voltage gains) = 15V with input terminals biased so that Terminal 6 potential is +7.5V above Terminal 4. 6. Total supply voltage (for indicated voltage gains) = 15V with output terminal driven to either supply rail.
+ 3 INPUT 2 AV 5X AV 6000X AV 30X
OUTPUT 6
-
4 CC COMPENSATION (WHEN DESIRED)
V-
5
1
8
STROBE
OFFSET NULL
3-4
CA5160 Schematic Diagram
BIAS CIRCUIT CURRENT SOURCE FOR Q6 AND Q7 "CURRENT SOURCE LOAD" FOR Q11 7 V+
Q1 D1 Z1 8.3V R1 40k R2 5k INPUT STAGE D5 NON-INV. INPUT 3 2 + D2 D3 D4
Q2
Q3
Q4
Q5
D6
D7
SECOND STAGE OUTPUT STAGE
Q8 OUTPUT 6
Q6
Q7
2k R4 1k Q10 30 pF Q12
R3 1k Q9
INV. INPUT
Q11
R5 1k
R6 1k SUPPLEMENTARY COMP IF DESIRED
5 OFFSET NULL
1
8 STROBING
4
NOTE: Diodes D5 through D7 provide gate oxide protection for MOSFET Input Stage.
Application Information
Circuit Description Refer to the block diagram of the CA5160 CMOS Operational Amplifier. The input terminals may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA5160 circuit is ideal for single supply operation. Three class A amplifier stages, having the individual gain capability and current consumption shown in the block diagram, provide the total gain of the CA5160. A biasing circuit provides two potentials for common use in the first and second stages. Terminals 8 and 1 can be used to supplement the internal phase compensation network if additional phase compensation or frequency roll-off is desired. Terminals 8 and 4 can also be used to strobe the output stage into a low quiescent current state. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply rail potential at Terminal 7. This condition of essentially zero current drain in the output stage under the strobed "OFF" condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g., when the amplifier output is used to drive CMOS digital circuits in comparator applications). Input Stages The circuit of the CA5160 is shown in the schematic diagram. It consists of a differential input stage using PMOS field effect transistors (Q6, Q7) working into a mirror pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirror pair transistors also function as a differential-to-single-ended converter to provide base drive to the second-stage bipolar transistor (Q11). Offset nulling, when desired, can be effected by connecting a 100,000 potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4. Cascode-connected PMOS transistors Q2, Q4, are the constant current source for the input stage. The biasing circuit for the constant current source is subsequently described. The small diodes D5 through D7 provide gateoxide protection against high voltage transients, including static electricity during handling for Q6 and Q7. Second Stage Most of the voltage gain in the CA5160 is provided by the second amplifier stage, consisting of bipolar transistor Q11 and its cascode-connected load resistance provided by
3-5
CA5160
PMOS transistors Q3 and Q5. The source of bias potentials for these PMOS transistors is described later. Miller Effect compensation (roll off) is accomplished by means of the 30pF capacitor and 2k resistor connected between the base and collector of transistor Q11. These internal components provide sufficient compensation for unity gain operation in most applications. However, additional compensation, if desired, may be used between Terminals 1 and 8. Bias-Source Circuit At total supply voltages, somewhat above 8.3V, resistor R2 and zener diode Z1 serve to establish a voltage of 8.3V across the series connected circuit, consisting of resistor R1, diodes D1 through D4, and PMOS transistor Q1. A tap at the junction of resistor R1 and diode D4 provides a gate bias potential of about 4.5V for PMOS transistors Q4 and Q5 with respect to Terminal 7. A potential of about 2.2V is developed across diode connected PMOS transistor Q1 with respect to Terminal 7 to provide gate bias for PMOS transistors Q2 and Q3. It should be noted that Q1 is "mirror connected" to both Q2 and Q3. Since transistors Q1, Q2 and Q3 are designed to be identical, the approximately 200A current in Q1 establishes a similar current in Q2 and Q3 as constant current sources for both the first and second amplifier stages, respectively. At total supply voltages somewhat less than 8.3V, zener diode Z1 becomes non-conductive and the potential, developed across series connected R1, D1-D4, and Q1 varies directly with variations in supply voltage. Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in accordance with supply voltage variations. This variation results in deterioration of the power supply rejection ration (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance. Output Stage The output stage consists of a drain loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance loads, the output can be swung within millivolts of either supply rail. Because the output stage is a drain loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 20. Typical op-amp loads are readily driven by the output stage. Because large signal excursions are nonlinear, requiring feedback for good waveform reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01% accuracy levels, including the negative supply rail. Offset Nulling Offset voltage nulling is usually accomplished with a 100,000 potentiometer connected across Terminals 1 and 5 and with the potentiometer slider arm connected to Terminal 4. A fine offset null adjustment usually can be affected with the slider arm positioned in the mid point of the potentiometer's total range. Input Current Variation with Common Mode Input Voltage As shown in the Table of Electrical Specifications, the input current for the CA5160 Series Op Amps is typically 5pA at TA = 25oC when Terminals 2 and 3 are at a common-mode potential of +7.5V with respect to negative supply Terminal 4. Figure 1 contains data showing the variation of input current as a function of common-mode input voltage at TA = 25oC. These data show that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pA, provided the common-mode input voltage does not exceed 2V. As previously noted, the input current is essentially the result of the leakage current through the gateprotection diodes in the input circuit and, therefore, a function of the applied voltage. Although the finite resistance of the glass terminal-to-case insulator of the metal can package also contributes an increment of leakage current, there are useful compensating factors. Because the gateprotection network functions as if it is connected to Terminal 4 potential, and the metal can case of the CA5160 is also internally tied to Terminal 4, input terminal 3 is essentially "guarded" from spurious leakage currents.
10 TA = 25oC
7.5 INPUT VOLTAGE (V) V+ 15V TO 5V 7 CA5160 3 2.5 VIN 4 8 0V TO -10V V-1 0 1 2 3 4 5 6 7 6
5 PA
2
0 INPUT CURRENT (pA)
FIGURE 1. CA5160 INPUT CURRENT vs COMMON MODE VOLTAGE
Input Current Variation with Temperature The input current of the CA5160 series circuits is typically 5pA at 25oC. The major portion of this input current is due to leakage current through the gate protective diodes in the input circuit. As with any semiconductor-junction device, including op amps with a junction-FET input stage, the leakage current approximately doubles for every 10oC increase in temperature. Figure 2 provides data on the typical variation of input bias current as a function of temperature in the CA5160. In applications requiring the lowest practical input current and incremental increases in current because of "warm-up" effects, it is suggested that an appropriate heat sink be used with the CA5160. In addition, when "sinking" or "sourcing" significant output current the chip temperature increases, causing an increase in the input current. In such cases, heatsinking can also very markedly reduce and stabilize input current variations.
3-6
CA5160
4000 1000 INPUT CURRENT (pA)
Power Supply Considerations
VS = 7.5V
100
Because the CA5160 is very useful in single-supply applications, it is pertinent to review some considerations relating to power-supply current consumption under both single-and dual-supply service. Figures 4A and 4B show the CA5160 connected for both dual and single-supply operation. Dual-supply Operation: When the output voltage at Terminal 6 is 0V, the currents supplied by the two power supplies are equal. When the gate terminals of Q8 and Q12 are driven increasingly positive with respect to ground, current flow through Q12 (from the negative supply) to the load is increased and current flow through Q8 (from the positive supply) decreases correspondingly. When the gate terminals of Q8 and Q12 are driven increasingly negative with respect to ground, current flow through Q8 is increased and current flow through Q12 is decreased accordingly. Single Supply Operation: Initially, let it be assumed that the value of RL is very high (or disconnected), and that the inputterminal bias (Terminals 2 and 3) is such that the output terminal (Number 6) voltage is at V+/2, i.e., the voltage-drops across Q8 and Q12 are of equal magnitude. Figure 21 shows typical quiescent supply-current vs supply-voltage for the CA5160 operated under these conditions. Since the output stage is operating as a Class A amplifier, the supply-current will remain constant under dynamic operating conditions as long as the transistors are operated in the linear portion of their voltage transfer characteristics (see Figure 20). If either Q8 or Q12 are swung out of their linear regions toward cutoff (a nonlinear region), there will be a corresponding reduction in supply-current. In the extreme case, e.g., with Terminal 8 swung down to ground potential (or tied to ground), NMOS transistor Q12 is completely cut off and the supply-current to series-connected transistors Q8, Q12 goes essentially to zero. The two preceding stages in the CA5160, however, continue to draw modest supply-current (see the lower curve in Figure 21) even through the output stage is strobed off. Figure 4A shows a dual-supply arrangement for the output stage that can also be strobed off, assuming RL = , by pulling the potential of Terminal 8 down to that of Terminal 4. Let it now be assumed that a load-resistance of nominal value (e.g., 2k) is connected between Terminal 6 and ground in the circuit of Figure 4B. Let it further be assumed again that the input terminal bias (Terminals 2 and 3) is such that the output terminal (Number 6) voltage is V+/2. Since PMOS transistor Q8 must now supply quiescent current to both RL and transistor Q12, it should be apparent that under these conditions the supply current must increase as an inverse function of the RL magnitude. Figure 27 shows the voltage drop across PMOS transistor Q8 as a function of load current at several supply voltages. Figure 20 shows the voltage transfer characteristics of the output stage for several values of load resistance.
10
1 -80 -60 -40 -20 0 20 40 60 80 TEMPERATURE (oC) 100 120 140
FIGURE 2. INPUT CURRENT vs TEMPERATURE
Input Offset Voltage (VIO) Variation with DC Bias vs Device Operating Life It is well known that the characteristics of a MOSFET device can change slightly when a DC gate-source bias potential is applied to the device for extended time periods. The magnitude of the change is increased at high temperatures. Users of the CA5160 should be alert to the possible impacts of this effect if the application of the device involves extended operation at high temperatures with a significant differential DC bias voltage applied across Terminals 2 and 3. Figure 3 shows typical data pertinent to shifts in offset voltage encountered with CA5160 devices in metal can packages during life testing. At lower temperatures (metal can and plastic) for example at 85oC, this change in voltage is considerably less. In typical linear applications where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. The 2VDC differential voltage example represents conditions when the amplifier output state is "toggled", e.g., as in comparator applications.
7 TA = 125oC FOR METAL CAN PACKAGES 6 OFFSET VOLTAGE SHIFT (mV) DIFFERENTIAL DC VOLTAGE 5 (ACROSS TERMINALS 2 AND 3) = 2V OUTPUT STAGE TOGGLED 4 3 2 1 0 0 500 1000 1500 2000 2500 TIME (HOURS) 3000 3500 4000 DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 0V OUTPUT VOLTAGE = V+/2
FIGURE 3. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE
3-7
CA5160
Wideband Noise
V+ 7 3 +
Q8
OUTPUT STAGE
6 RL
2
4 8
Q12
V-
FIGURE 4A. DUAL POWER-SUPPLY OPERATION
From the standpoint of low-noise performance considerations, the use of the CA5160 is most advantageous in applications where in the source resistance of the input signal is on the order of 1M or more. In this case, the total inputreferred noise voltage is typically only 40V when the testcircuit amplifier of Figure 5 is operated at a total supply voltage of 15V. This value of total input-referred noise remains essentially constant, even though the value of source resistance is raised by an order of magnitude. This characteristic is due to the fact that reactance of the input capacitance becomes a significant factor in shunting the source resistance. It should be noted, however, that for values of source resistance very much greater than 1M, the total noise voltage generated can be dominated by the thermal noise contributions of both the feedback and source resistors.
+7.5V
RS V+ 1M 7 2 3 +
0.01F 7 6 NOISE VOLTAGE OUTPUT 30.1k
-
4 0.01 F
3
+
Q8
OUTPUT STAGE 6 RL BW (-3dB) = 200kHz TOTAL NOISE VOLTAGE (INPUT REFERRED) = 40V (TYP) -7.5V
2
4 8
Q12
1k
FIGURE 4B. SINGLE POWER-SUPPLY OPERATION FIGURE 4. CA5160 OUTPUT STAGE IN DUAL AND SINGLE POWER SUPPLY OPERATION
FIGURE 5. TEST-CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENTS
Typical Applications
Voltage Followers Operational amplifiers with very high input resistances, like the CA5160, are particularly suited to service as voltage followers. Figure 6 shows the circuit of a classical voltage follower, together with pertinent waveforms using the CA5160 in a split supply-configuration. A voltage follower, operated from a single-supply, is shown in Figure 7 together with related waveforms. This follower circuit is linear over a wide dynamic range, as illustrated by the reproduction of the output waveform in Figure 7B with input signal ramping. The waveforms in Figure 7C show that the follower does not lose its input-to-output phase-sense, even though the input is being swung 7.5V below ground potential. This unique characteristic is an important attribute in both operational amplifier and comparator applications. Figure 7C also shows the manner in which the CMOS output stage permits the output signal to swing down to the negative supply rail potential (i.e., ground in the case shown). The digital-toanalog converter (DAC) circuit, described in the following section, illustrates the practical use of the CA5160 in a singlesupply voltage follower application.
+7.5V
0.01F 3 10k 2 7 + 6
-
4 2k 0.01 F -7.5V 2k 25pF SIMULATED LOAD CAPACITANCE
BW (-3dB) = 4MHz SR = 10V/s
0.1F
FIGURE 6A. DUAL SUPPLY FOLLOWER
3-8
CA5160
with series and parallel combinations of 806,000 resistors from the same manufacturing lot. A single 15V supply provides a positive bus for the CA5160 follower amplifier and feeds the CA3085 voltage regulator. A "scaleadjust" function is provided by the regulator output control, set to a nominal 10V level in this system. The line-voltage regulation (approximately 0.2%) permits a 9 bit accuracy to be maintained with variations of several volts in the supply. The flexibility afforded by the CMOS building blocks simplifies the design of DAC systems tailored to particular needs.
Error Amplifier in Regulated Power Supplies
The CA5160 is an ideal choice for error-amplifier service in regulated power supplies since it can function as an error-amplifier when the regulated output voltage is required to approach 0V.
Top Trace: Output Bottom Trace: Input FIGURE 6B. SMALL SIGNAL RESPONSE
The circuit shown in Figure 9 uses a CA5160 as an error amplifier in a continuously adjustable 1A power supply. One of the key features of this circuit is its ability to regulate down to the vicinity of zero with only one DC power supply input. An RC network, connected between the base of the output drive transistor and the input voltage, prevents "turn-on overshoot", a condition typical of many operational-amplifier regulator circuits. As the amplifier becomes operational, this RC network ceases to have influence on the regulator performance. NOTE: "Digital-to-Analog Conversion Using the Intersil CD4007A CMOS IC", Application Note AN6080.
+15V 0.01F 6 2
3 10k
+
7
5 1
4 100k OFFSET ADJUST 2k 0.1F
Top Trace: Output Signal Center Trace: Difference Signal 5mV/Div. Bottom Trace: Input Signal FIGURE 6C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME FIGURE 6. SPLIT SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS
FIGURE 7A. SINGLE SUPPLY FOLLOWER
9 Bit CMOS DAC
A typical circuit of a 9 bit Digital-to-Analog Converter (DAC) (see Note) is shown in Figure 8. This system combines the concepts of multiple-switch CMOS ICs, a low cost ladder network of discrete metal-oxide-film resistors, a CA5160 op amp connected as a follower, and an inexpensive monolithic regulator in a simple single power supply arrangement. An additional feature of the DAC is that it is readily interfaced with CMOS input logic, e.g., 10V logic levels are used in the circuit of Figure 8. The circuit uses an R/2R voltage-ladder network, with the outputpotential obtained directly by terminating the ladder arms at either the positive or the negative power-supply terminal. Each CD4007A contains three "inverters", each "inverter" functioning as a singlepole double-throw switch to terminate an arm of the R/2R network at either the positive or negative power-supply terminal. The resistor ladder is an assembly of 1% tolerance metal-oxide film resistors. The five arms requiring the highest accuracy are assembled
0
FIGURE 7B. OUTPUT SIGNAL WITH INPUT SIGNAL RAMPING
3-9
CA5160
Precision Voltage-Controlled Oscillator The circuit diagram of a precision voltage-controlled oscillator is shown in Figure 10. The oscillator operates with a tracking error on the order of 0.02% and a temperature coefficient of 0.01%/oC. A multivibrator (A1) generates pulses of constant amplitude (V) and width (T2). Since the output (Terminal 6) of A1 (a CA5130) can swing within about 10mV of either supply-rail, the output pulse amplitude (V) is essentially equal to V+. The average output voltage (EAVG = V T2/T1) is applied to the noninverting input terminal of comparator A2 (a CA5160) via an integrating network R3, C2. Comparator A2 operates to establish circuit conditions such that EAVG = V1. This circuit condition is accomplished by feeding an output signal from Terminal 6 of A2 through R4, D4 to the inverting terminal (Terminal 2) of A1, thereby adjusting the multivibrator interval, T3. Voltmeter With High Input Resistance The voltmeter circuit shown in Figure 11 illustrates an application in which a number of the CA5160 characteristics are exploited. Range-switch SW1 is ganged between input and output circuitry to permit selection of the proper output voltage for feedback to Terminal 2 via 10k current-limiting resistor. The circuit is powered by a single 8.4V mercury battery. With zero input signal, the circuit consumes somewhat less than 500A plus the meter current required to indicate a given voltage. Thus, at full-scale input, the total supply current rises to slightly more than 1500A.
0
0
Top Trace: Output Bottom Trace: Input FIGURE 7C. OUTPUT-WAVEFORM WITH GROUND-REFERENCE SINE-WAVE INPUT FIGURE 7. SINGLE SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS (e.g., FOR USE IN SINGLE-SULLPL D/A CONVERTER; SEE FIGURE 9 IN AN6080)
10V LOGIC INPUTS +10.010V LSB 9 6 14 8 3 7 10 11 2 CD4007A "SWITCHES" 9 7 4 13 8 806K 1% 806K 1% 1 5 402K 1% 200K 1% 12 13 8 100K 1% 806K 1% CD4007A "SWITCHES" 1 5 806K 1% 750K 1% 806K 1% 12 13 8 (2) 806K 1% CD4007A "SWITCHES" 1 5 (4) 806K 1% (8) 806K 1% +15V PARALLELED RESISTORS OUTPUT VOLTAGE REGULATOR 2 CA3085 3 7 4 + 2F 25V 6 1 8 22.1K 1% REGULATED VOLTAGE ADJUST 3.83K 1% 1K 0.001F 6 62 +10.010V 7 + CA5160 4 LOAD 5 1 100K OFFSET NULL 2K 0.1F 3 VOLTAGE FOLLOWER 2 10K 12 6 6 5 3 4 10 3 6 2 3 MSB 1 10
+15V
BIT 1 2 3 4 5 6-9
REQUIRED RATIOMATCH Standard 0.1% 0.2% 0.4% 0.8% 1% ABS.
-
-
FIGURE 8. 9 BIT DAC USING CMOS DIGITAL SWITCHES AND CA5160
3-10
CA5160
2N6385 POWER DARLINGTON INPUT 40V + 3 2 10k 0.2F TURN ON DELAY 2.4k 1W 100k 1.5k 1W 1k 1 1N914 56pF 2.2k 7 100F 25V + + 5F CA3086 10 11 2 1 5 1 9 8 7 6 3 5 4 1k 50k 62k 0.01F 100k 12 14 13 10k 4 8 10k + 6 3 43k + 100F 1k OUTPUT 0V 35V AT 1A 1 SHORT-CIRCUIT CURRENT LIMIT ADJUSTMENT
2N2102
-
-
-
2k
-
2 8.2 k
4.7k
Hum and Noise Output <250VRMS; Regulation (No Load to Full Load) <0.005%; Input Regulation <0.01%/V FIGURE 9. CA5160 VOLTAGE REGULATOR CIRCUIT (0.1 TO 35V AT 1A)
T2 +15V V T1 D1 10K 1M 0.01F +15V 100K D2 7 3 R6 100K C1 500pF 2 + A1 MULTIVIBRATOR CA5130 6 R3 1M 4 C2 0.01F R1 182K 3 0.1 F +15V T3 fo VCO CONTROL VOLTAGE (VI) (0V - 10V) (SENSITIVITY = 1kHz/V)
-
R5 100K
2 EAVG = V T2/T1
A2 COMPARATOR CA5160 + 5 1 R7 100K
7
6
-
4 0.01F
D3 R2 10K
D4
D5 R4 3K
D1 - D5 = 1N914
FIGURE 10. VOLTAGE CONTROLLED OSCILLATOR
3-11
CA5160
BATTERY TEST OFF ON
300V 100V 30V 10V
100M
300V 100V 30V
1.02 M
10V
9.9 k +9V BATTERY 3 22M 0.001 F 2 7 + CA5160
3 POSITION SLIDE SWITCH +
BATTERY 3V CAL. 500 300V 100V 820 200 30V 10V 3V 1V 300mV 9k 100mV 30mV 10mV 100 SW1A 3V INPUT 1V 300mV 100mV 30mV 10mV 3V 1V 300mV 100mV 30mV 10mV 100k 9.1k ZERO ADJUST 10k SW1B
500 F M 0-1mA
2.7k 6 4 5 300V 100V 30V 10V SW1C 3V 1V 300mV 100mV 30mV 10mV 900
1
1V CAL.
SW1D
FIGURE 11. CA5160A HIGH INPUT RESISTANCE DC VOLTMETER
8.2k 20pF VOLTAGE-CONTROLLED CURRENT SOURCE 7 3 1k 2 1k 2M -7.5V SYMMETRY -7.5V 100k +7.5V 4.7k + CA3080A 6 4 5 +7.5V
BUFFER VOLTAGE FOLLOWER 0.9 - 7pF C1 +7.5V HIGH FREQ. SHAPE 3 + 6 -7.5V
CENTERING 100k 430pF 0.1F
THRESHOLD DETECTOR +7.5V 30k +7.5V
7
6.8M 5 10k 7 2
6.2k
-
10-80pF C2
4 - 60pF CA5160 C3 2 4
CA3080 6 4 -7.5V +
3
EXTERNAL SWEEPING INPUT -7.5V
0.1 F C4 4 - 60pF 2k HIGH FREQ LEVEL ADJUST
10k
50k C5 15 - 115pF
2-1N914
MAX FREQ SET 7.5V 10k 6.2k
MIN. FREQ. SET -7.5V 500 FREQ ADJUST 500
FIGURE 12A. FUNCTION GENERATOR CIRCUIT
3-12
CA5160
NOTE: A square wave signal modulates the external sweeping input to produce 1Hz and 1MHz, showing the 1,000,000/1 frequency range of the function generator. FIGURE 12B. TWO-TONE OUTPUT SIGNAL FROM THE FUNCTION GENERATOR
NOTE: The bottom trace is the sweeping signal and the top trace is the actual generator output. The center trace displays the 1MHz signal via delayed oscilloscope triggering of the upper swept output signal. FIGURE 12C. TRIPLE-TRACE OF THE FUNCTION GENERATOR SWEEPING TO 1MHz
FIGURE 12. CA5160 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR - 1MHz TO 1Hz
+15V +15V 100 k 100 k 1M 3 100 k 2 15 - 115pF FREQ ADJUST + CA5130 6 8 1N914 3 4 7 STEP HEIGHT ADJUST 4 - 60pF 8.2k 2 470pF
5.1k
1N914 STAIRCASE OUTPUT 7 10k
+15V 7
+15V
CA5160 + 4 6 2k
-
3 +15V 1.5 M 2
+ CA5130 6 8 4
-
MULTIVIBRATOR
CHARGE COMMUTATING NETWORK MULTIVIBRATOR RETRACE INHIBIT
INTEGRATOR HYSTERESIS SWITCH 51k
+15mV TO +10V
100k
FIGURE 13A. STAIRCASE GENERATOR CIRCUIT
3-13
CA5160
Function Generator A function generator having a wide tuning range is shown in Figure 12. The adjustment range, in excess of 1,000,000/1, is accomplished by a single potentiometer. Three operational amplifiers are utilized: a CA5160 as a voltage follower, a CA3080 as a high-speed comparator, and a second CA3080A as a programmable current source. Three variable capacitors C1, C2, and C3 shape the triangular signal between 500kHz and 1MHz. Capacitors C4, C5, and the trimmer potentiometer in series with C5 maintain essentially constant (10%) amplitude up to 1MHz. Staircase Generator
Top Trace: Staircase Output 2V Steps Center Trace: Comparator Bottom Trace: Oscillator FIGURE 13B. STAIRCASE GENERATOR WAVEFORM FIGURE 13. STAIRCASE GENERATOR CIRCUIT UTILIZING THREE CMOS OPERATIONAL AMPLIFIERS
STAIRCASE OUTPUT 2V STEPS COMPARATOR
OSCILLATOR
Figure 13 shows a staircase generator circuit utilizing three CMOS operational amplifiers. Two CA5130s are used; one as a multivibrator, the other as a hysteresis switch. The third amplifier, a CA5160, is used as a linear staircase generator.
+15V 0.1F 10M 7 3 + CA5160 2 6
10G 1M 10pF 7 2 10k 4 +15V
CA3140 6 9.9k 5.6k 500 100 M 500-0-500A + 4 0.1F
5 1
3 560k
100k 9.1k
-15V
-15V
FIGURE 14. CURRENT-TO-VOLTAGE CONVERTER TO PROVIDE A PICOAMMETER WITH 3pA FULL SCALE DEFLECTION
+15V
100k
+15V 2200pF
30pF 7 1M 3 + CA5160 2 6 8 4 5 1 100k 8.2k OFFSET VOLTAGE ADJUST 2k 9.1k 27k 500A STROBE INPUT 0.1F 3 2 0.1F
0.1 F 39k 7 8.2
+15V
-
1N914 CA3080A + 4 5 DROOP ZERO ADJUST 39k 100k 6 1M 0.1 F 2 3
7
CA3140 + 4 6
SAMPLE - 15V HOLD - 0V
FIGURE 15A. SAMPLE AND HOLD CIRCUIT
3-14
CA5160
SAMPLED OUTPUT
SAMPLED OUTPUT 0VINPUT 0V-
INPUT SIGNAL SAMPLING PULSES
SAMPLING PULSE
Top Trace: Sampled Output Center Trace: Input Signal Bottom Trace: Sampling Pulses FIGURE 15B. SAMPLE AND HOLD WAVEFORM
Top Trace: Sampled Output Center Trace: Input Bottom Trace: Sampling Pulses FIGURE 15C. SAMPLE AND HOLD WAVEFORM
FIGURE 15. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V
Picoammeter Circuit Figure 14 is a current-to-voltage converter configuration utilizing a CA5160 and CA3140 to provide a picoampere meter for 3pA full-scale meter deflection. By placing Terminals 2 and 4 of the CA5160 at ground potential, the CA5160 input is operated in the "guarded mode". Under this operating condition, even slight leakage resistance present between Terminals 3 and 2 or between Terminals 3 and 4 would result in 0V across this leakage resistance, thus substantially reducing the leakage current. If the CA5160 is operated with the same voltage on input Terminals 3 and 2 as on Terminal 4, a further reduction in the input current to the less than 1pA level can be achieved as shown in Figure 1. To further enhance the stability of this circuit, the CA5160 can be operated with its output (Terminal 6) near ground, thus markedly reducing the dissipation by reducing the supply current to the device. The CA3140 stage serves as a X100 gain stage to provide the required plus and minus output swing for the meter and feedback network. A 100-to-1 voltage divider network consisting of a 9.9k resistor in series with a 100 resistor sets the voltage at the 10G resistor (in series with Terminal 3) to 30mV full-scale deflection. This 30mV signal results from 3V appearing at the top of the voltage divider network which also drives the meter circuitry. By utilizing a switching technique in the meter circuit and in the 9.9k and 100 network similar to that used in the voltmeter circuit shown in Figure 11, a current range of 3pA to 1nA full scale can be handled with the single 10G resistor.
Single Supply Sample-and-Hold System
CA3140 output integrator and storage capacitor. The CA3140 was chosen because of its low output impedance and constant gain-bandwidth product. Pulse "droop" during the hold interval can be reduced to zero by adjusting the 100k biasvoltage potentiometer on the positive input of the CA3140. This zero adjustment sets the CA3080A output voltage at its zero current position. In this sample-and-hold circuit it is essential that the amplifier bias current be reduced to zero to minimize output signal current during the hold mode. Even with 320mV at the amplifier bias circuit (Terminal 5) at least 100pA of output current will be available.
+15V R1 100k C2 51pF 3 2 R2 100k C1 10-80pF + CA5160 6 4 2k 2-1N914 0.01F 680 f= 1 2 (R1 || R2) C1 R3 C2 500 R3 51k 7 +15V 0.1 F OUTPUT f = 100kHz 2% THD AT 1.1VP-P
-
FIGURE 16. SINGLE-SUPPLY WEIN BRIDGE OSCILLATOR
Wien Bridge Oscillator
Figure 15 shows a single-supply sample-and-hold system using a CA5160 to provide a high input impedance and an input-voltage range of 0V to 10V. The output from the input buffer integrator network is coupled to a CA3080A. The CA3080A functions as a strobeable current source for the
A simple, single-supply Wien Bridge oscillator using a CA5160 is shown in Figure 16. A pair of parallel-connected 1N914 diodes comprise the gain-setting network which standardizes the output voltage at approximately 1.1V. The 500 potentiometer is adjusted so that the oscillator will always start and the oscillation will be maintained. Increasing the amplitude of the
3-15
CA5160
voltage may lower the threshold level for starting and for sustaining the oscillation, but will introduce more distortion. Operation with Output-Stage Power-Booster The current sourcing and sinking capability of the CA5160 output stage is easily supplemented to provide power-boost capability. In the circuit of Figure 17, three CMOS transistor-pairs in a single CA3600 lC array are shown parallel-connected with the output stage in the CA5160. In the Class A mode of CA3600E shown, a typical device consumes 20mA of supply current at 15V operation. This arrangement boosts the current-handling capability of the CA5160 output stage by about 2.5X. The amplifier circuit in Figure 17 employs feedback to establish a closed-loop gain of 20dB. The typical large-signalbandwidth (-3dB) is 190kHz.
+15V 14 CA3600 (NOTE) QP1 2 11
0.01F
-
1F
1M + 3 +
7
QP2
QP3
680k INPUT 2 1F 2k
CA5160
6 8 6
13
1 500F
4
3
10
12 50 100mW AT 10% THD QN3
8 A = 20dB LARGE SIGNAL BW (-3dB) = 190kHz QN1 QN2
5
7
4
9
NOTE: See File Number 619.
20k
FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA5160.
Typical Performance Curves
OPEN-LOOP VOLTAGE GAIN (dB)
OPEN-LOOP VOLTAGE GAIN (dB)
100
VS = 7.5V TA = 25oC
OPEN-LOOP PHASE (DEGREES)
120
150 RL = 2k 140 130 120 110 100 90 80 -100
0 50 100
80
OL
150 200
60
40
CL = 30pF RL = 2k
20
0 101 102 103 104 105 106 FREQUENCY (Hz) 107 108
-50
0 50 TEMPERATURE (oC)
100
FIGURE 18. OPEN-LOOP VOLTAGE GAIN AND PHASE SHIFT vs FREQUENCY
FIGURE 19. OPEN-LOOP GAIN vs TEMPERATURE
3-16
CA5160 Typical Performance Curves
OUTPUT VOLTAGE [TERMS 4 AND 6] (V) 17.5 15 12.5 1k 10 7.5 5 2.5 0 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 GATE VOLTAGE (TERMINALS 4 AND 8) (V) 500 QUIESCENT SUPPLY CURRENT (mA) SUPPLY VOLTAGE: V+ = 15V, V- = 0V TA = 25oC LOAD RESISTANCE = 5k 2k
(Continued)
15 12.5 LOAD RESISTANCE = TA = 25oC OUTPUT VOLTAGE BALANCED = V+/2 V- = 0
10
7.5
5 OUTPUT VOLTAGE HIGH = V+ OR LOW = V2.5 0 6 8 10 12 14 16 POSITIVE SUPPLY VOLTAGE (V) 18
FIGURE 20. VOLTAGE TRANSFER CHARACTERISTICS OF CMOS OUTPUT STAGE
FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
14 QUIESCENT SUPPLY CURRENT (mA) 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 POSITIVE SUPPLY VOLTAGE (V) OUTPUT VOLTAGE = V+/2 V- = 0 TA = -55oC 25oC 125oC SUPPLY CURRENT (A)
600 V+ = 5V, V- = 0V 525 450 375 300 225 150 75 0 0 0.5 1 1.5 2 2.5 3 3.5 OUTPUT VOLTAGE (V) 4 4.5 5 -55oC 125oC 25oC
FIGURE 22. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 23. SUPPLY CURRENT vs OUTPUT VOLTAGE
8 V+ = 5V, V- = 0V OUTPUT VOLTAGE SWING (V) 7 OUTPUT VOLTAGE SWING (V) 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 LOAD RESISTANCE (k) 9 10 11 -55oC 25oC 125oC
9 V+ = 5V, V- = 0V 8 7 6 5 4 3 2 1 0 0.1 0.2 0.6 1 4 68 20 40 80 2 LOAD RESISTANCE (k) 200 800
FIGURE 24. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
FIGURE 25. OUTPUT SWING vs LOAD RESISTANCE
3-17
CA5160 Typical Performance Curves
8 V+ = 5V, V- = 0V 7 OUTPUT CURRENT (mA) 6 5 4 SINK 3 2 SOURCE 1 0 -60 VOLTAGE DROP ACROSS PMOS OUTPUT STAGE TRANSISTOR (Q8) (V)
(Continued)
50 10
V- = 0V TA = 25oC V+= 5V
10V
15V
1
0.1
0.01
-40
-20
0
20
40
60
80
100 120 140
0.001 0.001
0.01
0.1
1
10
100
TEMPERATURE (oC)
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 26. OUTPUT CURRENT vs TEMPERATURE
FIGURE 27. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR (Q8) vs LOAD CURRENT
1000
VOLTAGE DROP ACROSS NMOS OUTPUT - STAGE TRANSISTOR (Q12) (V)
50 10 V- = 0V TA = 25oC V+ = 15V 10V 5V
TA = 25oC VS = 7.5V
INPUT NOISE VOLTAGE (nV/ Hz) 1 10 100
1
100
0.1
10
0.01
0.001 0.001
0.01
0.1
1 1
101
MAGNITUDE OF LOAD CURRENT (mA)
102 103 FREQUENCY (Hz)
104
105
FIGURE 28. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR (Q12) vs LOAD CURRENT
FIGURE 29. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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3-18

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